The invention relates to a current mirror comprising:
a first terminal for receiving an input current; PA1 a second terminal for supplying an output current; PA1 a common terminal; PA1 a first transistor having a control electrode, and having a main current path arranged between the first terminal and the common terminal; PA1 a second transistor having a control electrode connected to the control electrode of the first transistor, and having a main current path arranged between the second terminal and the common terminal. PA1 a transconductance stage having an input terminal coupled to the first terminal, and having an output terminal coupled to the common terminal; PA1 and a bias source for biassing the control electrode of the first transistor and the control electrode of the second transistor.
Such a current mirror is known, for example, from U.S. Pat. No. 4,462,005 and is shown in FIG. 1. In this well-known basic current mirror the interconnected control electrodes, in this case the bases, of the first transistor T1 and the second transistor T2 are connected to the first terminal which forms the current input terminal of the current mirror. The common terminal is connected to a reference terminal, in this case the negative supply terminal which serves as signal ground. As will be explained hereinafter, the bandwidth of this known current mirror strongly depends on the input current due to the presence of an input capacitance C.sub.i between the first terminal and the common terminal and of base-emitter capacitances C.sub.be of the first and the second transistor T1 and T2. By adding degeneration resistors in series with the emitters of the first and the second transistor T1 and T2, as shown in FIG. 2, the dependence on the input current can be avoided to some extent. However, this comes at the cost of a reduced bandwidth, an increased input impedance and a smaller voltage swing in comparison with to the basic current mirror of FIG. 1.
It is known to obtain an improvement in bandwidth by adding a gain stage GS as shown in FIG. 3. FIG. 4 shows gain stage formed by means of an emitter follower EF between the first terminal and the interconnected control electrodes of the first and the second transistor T1 and T2. This improved current mirror still has a bandwidth which depends on the input current.